Electrostatic clamps or chucks (ESCs) are often utilized in the semiconductor industry for clamping substrates during, for example, plasma-based and/or vacuum-based semiconductor processes such as etching, CVD, and ion implantation, etc. Capabilities of the ESCs, including non-edge exclusion and wafer temperature control, have proven to be quite valuable in processing semiconductor substrates or wafers, such as silicon wafers. A typical ESC, for example, comprises a dielectric layer positioned over a conductive electrode, wherein the semiconductor wafer is placed on a surface of the ESC (e.g., the wafer is placed on a surface of the dielectric layer). During semiconductor processing (e.g., plasma processing), a clamping voltage is typically applied between the wafer and the electrode, wherein the wafer is clamped against the chuck surface by electrostatic forces.
A subset of electrostatic clamps, referred to as Johnsen-Rahbek (J-R) clamps, utilize “leaky” dielectric layers (e.g., semiconductive dielectric layers having bulk resistances of between approximately 1×109 to 1×1012 Ohm-cm) in contact with the wafer, wherein greater clamping forces can be achieved at lower voltages than with conventional non-J-R clamps. Lower voltage input to the ESC typically not only reduces power supply requirements associated with the J-R clamps, but further provides a clamping environment that is potentially less destructive to the wafer and devices formed thereon.
A conventional J-R clamp, for example, comprises a dielectric layer that is slightly conductive, thus generally permitting a thickness of the dielectric layer (e.g., a ceramic) to be thicker than would be permitted for a “classic” or Coulombic ESC. Such an increase in thickness greatly facilitates the clamp manufacturing process, while also reducing clamp operating voltages. For example the dielectric layer can be used as a base for the formation of positive and negative electrodes by screen printing and firing of a dielectric paste.
However, a charge transfer typically resulting from the use of a semiconductor dielectric, for example, can also transmit a charge to the wafer, therein generating residual clamping forces that can result in a delay in releasing the wafer from the clamp. To mitigate the effects of residual clamping forces, A/C clamping voltages utilizing multiple groups of electrodes (e.g., multi-phasing or poly-phasing) can be utilized to diminish the clamping forces. However, such A/C clamping voltages and multiple groups of electrodes typically necessitate that each electrode have its area distributed somewhat evenly across the clamp. The resulting electrode structures can be quite complicated and expensive because of the design constraints driven by the need to maximize clamping area and force.
Most wafer removal mechanisms remove the entire wafer perpendicular to the electrostatic clamp surface. The forces required to remove a wafer in this manner are significantly high and can result in damage to the wafer.
In addition, there is a need for greater throughput of wafers in production, often measured in wafers per hours. Rates have recently gone from 200 wafers produced per hour with companies pushing now for 400-500 wafers/hour. Wafer and ESC electrical discharge is typically a function of time, and the times necessary to allow a wafer to discharge to allow removal due to acceptable forces, for example were suitable in the 200 wafers/second range. However those electronic discharge rates are no longer acceptable for the higher throughputs. Consequently, a need exists to improve production time of wafers or wafer throughput.
Therefore, a need exists in the art for a mechanism and/or method that reduces the force required to remove the wafer from the electrostatic clamp, wherein reliability is increased, while also reducing production costs.